The invention relates to a switched phase dual-modulus prescaler or divider counter circuit for a frequency synthesizer. The circuit divides the frequency of at least one high-frequency signal by a first factor in a first selected mode and by a second factor in a second selected mode. It comprises a plurality of asynchronous dividers-by-two connected in series. One of the dividers-by-two is of the master-slave type for receiving two input signals in phase opposition, and for supplying four signals phase shifted by 90° in relation to each other. The circuit further comprises a phase selector unit inserted between two of the dividers-by-two for receiving the four phase shifted signals from the master-slave first divider and for supplying a selected one of the four phase shifted signals to the second divider. A control unit supplies control signals to the phase selector unit for selecting a phase shifted signal.
Frequency synthesizers are used to supply high-frequency signals in wireless communication systems, for example, and in telecommunication systems in general.
The high-frequency signals may be used to demodulate received RF signals, for example.
FIG. 1 represents one embodiment of a conventional frequency synthesizer with a dual-modulus prescaler circuit. The synthesizer includes a reference oscillator, not shown, which supplies a reference signal Fref at a stable frequency to a phase and frequency detector 2 which also receives a divided frequency signal Fdiv from a dual-modulus prescaler circuit 5 in order to compare the reference signal and the divided frequency signal. The detector supplies a comparison signal that is a function of the phase and frequency difference between the signals Fref and Fdiv to a low-pass filter 3 connected to a voltage-controlled oscillator (VCO) 4. This voltage controlled oscillator receives a voltage control signal originating from the low-pass filter so that the oscillator generates at least a high frequency signal dependent on the comparison between signals Fref and Fdiv.
The voltage-controlled oscillator may be a differential type oscillator supplying two high-frequency signals Fs and Fsb in phase opposition to the prescaler circuit 5 in a phase-locked loop. At least one of high frequency signals Fs or Fsb can thus be used for demodulation operations in a radio-frequency signal receiver for example.
The dual-mode prescaler circuit 5 performs frequency division by a division factor that depends on a selected mode. To this end, a logic circuit with two counters A and B is generally used to provide the prescaler circuit with a mode selection facility. The logic circuit 6, which is well known in this technical field, is controlled by a microprocessor and by the divided frequency signal Fdiv. The two counters A and B are in principle clocked synchronously by the same clock signal, but the number counted by each counter prior to a reset is different. This enables the logic circuit 6 to supply a mode signal to the prescaler circuit in order to change division mode in particular periods.
Several embodiments of dual-modulus type prescaler circuits have already been proposed, but since these circuits have to operate at high speed, they are more difficult to design than simple fixed division ratio frequency dividers. One problem is that, in achieving frequency division using first and second division factors, the logic part of the circuit slows down the whole of the circuit.
U.S. Pat. No. 6,067,339 describes one example of a conventional dual-modulus prescaler circuit. The division factor is either 64 or 65, on the one hand, or 128 or 130, on the other hand, depending on the mode selected. The circuit has a synchronous division first part for selecting the division factor and an asynchronous division second part. For that, the circuit therefore comprises a plurality of dividers-by-two connected in series. A unit made up of synchronous dividers divides by 4 or 5 and the other dividers are asynchronous.
The synchronous divider unit employs a certain number of logic gates to enable the circuit to divide the high-frequency signal by a selected one of the two division factors. The logic gates on the critical path of said synchronous divider unit may cause a reduction in the maximum input frequency. The unit comprises three D-type flip-flops clocked by the same clock signal, which is an output signal from a first divider-by-two. However, one of the flip-flops of this unit is used only to obtain the division factor of 65 or 130.
A synchronous divider unit of the above type is usually intended to receive the high-frequency signal directly. As a result, the flip-flops in the synchronous divider unit operate at a high frequency, which may be a disadvantage from the power consumption point of view in particular. A partial solution to this problem is the circuit described in U.S. Pat. No. 6,037,339, in which an asynchronous divider-by-two precedes the synchronous divider unit. However, the first divider merely divides by two the frequency of the high-frequency signal, which means that the flip-flops of the synchronous divider unit must operate at an even higher frequency.
Another disadvantage of this type of circuit is that fine adjustment of frequency division by the two division factors is not possible, in particular because a first divider-by-two is used to reduce the frequency of the high-frequency signal. It is therefore not possible to provide frequency divisions by division factors having a smaller difference between them.
An example of a dual-modulus prescaler circuit that avoids the use of a synchronous divider unit is described in an article by Mrs. Jan Craninckx and Michiel S. J. Steyaert published in the IEEE integrated circuit journal, Volume 31 of 7 Jul. 1996. Like the present invention, this dual-modulus prescaler circuit comprises only asynchronous dividers-by-two connected in series. This dual-modulus circuit therefore comprises a chain of seven asynchronous dividers-by-two that is interrupted by a phase selector unit to enable frequency division by 128 or by 129. Only the first divider-by-two operates at the highest frequency, i.e. the frequency of at least one received high-frequency signal Fin.
A master-slave second divider-by-two is connected to the first divider-by-two and supplies four signals phase shifted by 90° in relation to each other to the phase selector unit on the basis of two phase-opposition signals supplied by the first divider. Relative to the first of the four signals supplied by the master-slave divider, the other signals are therefore phase shifted by 90°, 180° and 270°. The selector unit comprises two differential amplifiers for amplifying and selecting the four phase shifted signals and selection means for supplying a selected one of the four signals at the output.
The selector unit is controlled by a control logic unit as a function of the mode selected. In a first selected mode, said circuit must divide the frequency of the high-frequency signals by a division factor equal to 128. In this case, in all division periods, the selector unit selects only one of the four signals. In a second selected mode, the circuit must divide the frequency of the high-frequency signals by a division factor equal to 129. To obtain this factor, phase switching between two of the four phase shifted signals is effected within the selector unit as a function of control signals produced by the control unit. In each division period, phase switching between a first signal supplied by the second divider and a second signal in a phase delay of 90° relative to that of the first signal is therefore obtained. To this end, the control unit is clocked by the output signal of the last divider-by-two so that control signals are supplied to the phase selector unit to effect the phase switching in each division period.
To modify the state of the control unit as a function of a selected mode, a NAND type logic gate receives the mode signal and the output signal from the last divider-by-two. If the value of the mode signal is 0, the variation of the output signal at the control unit has no effect. On the other hand, if the value of the mode signal is 1, the output signal is inverted by the NAND gate to clock the control unit and enable the selector unit to perform the signal phase switching. Note that the control portion of the selector unit is no longer entirely synchronous.
A major drawback of the solution described in the article by Mrs. Craninckx and Steyaert is that voltage drops may occur in the output signal of the selector unit on the occasion of phase switching in the second selected mode. These voltage drops are caused by the changeover in the selector unit from the first signal to the second signal, which is in phase delay of 90° in relation to the first signal. In this case, the division factor may no longer be equal to 129, and may be much lower than 128, because of a supplementary pulse in the output signal of the selector unit. To avoid this problem, which is caused by the fact that the logic part for supplying control signals does not react quickly enough, the frequency of the high-frequency signals supplied to the input of said circuit must be high. On the other hand, if the frequency of said high-frequency signals is not sufficiently high, voltage drops occur in the output signal at the time of phase switching.
To solve this problem, it is necessary to slow down the beginning and/or the slope of the transitions in the control signals supplied by the control unit. It may prove difficult to adjust the beginning and/or the slope of the transitions in the control signals to take account of the frequency of the high-frequency signals received that is to be divided.
As can be seen in FIG. 5a, if the control signal C0 from the selection means has a relatively steep transition slope I1, a high voltage drop occurs in the output signal F4. On the other hand, if the transition slope I2 is gentle, the voltage drop in the output signal F4 has virtually no further effect on the division factor. Nevertheless, it is clear that the circuit proposed in the article by Mrs. Jan Craninckx and Michiel S. J. Steyaert is not normally able to divide signals whose frequency is relatively low. The high-frequency signals must have a frequency higher than a particular minimum frequency. Moreover, the problem of voltage drops is also dependent on the supply voltage of the dual-modulus prescaler circuit. Because of this, the circuit can operate only between particular minimum and maximum voltages.